At the 10/100 Ethmac, the TxFIFO is synchronized with the Wishbone CLK.
The read(for the FIFO) signal crosses from the MTxClk to the TxFIFO by using the 2 flip-flops.

The data from the TxFIFO is not synchronized because it should be available long before is should be latched.

My question is about the latching of the first byte at the start of the frame,
if TxStartFrm_sync2 & ~TxStartFrm which indicates start of frame the data from the fifo directly latched to the output towards eth_txethmac module, so TxData_wb(fifo output) should be available at this stage.


but its seems that this is not the case because at the same clock ReadTxDataFromFifo_tck starts propogationg towards the FIFO so TxData_wb is not valid at this point

The documentation states that WBinterface sets TxStartFrm signal to 1 with first byte of data.

Do I understand something incorrectly ?

thanks,